Improving execution unit occupancy on SMT-based processors through hardware-aware thread scheduling

TitleImproving execution unit occupancy on SMT-based processors through hardware-aware thread scheduling
Publication TypeJournal Article
Year of Publication2014
AuthorsAchille Peternier, Danilo Ansaloni, Daniele Bonetta, Cesare Pautasso, and Walter Binder
JournalFuture Generation Computer Systems
Volume30
Pages229 - 241
MonthJanuary
ISSN0167739X
Keywordsmulticores, Overseer
Abstract

Modern processor architectures are increasingly complex and heterogeneous, often requiring software solutions tailored to the specific hardware characteristics of each processor model. In this article, we address this problem by targeting two processors featuring Simultaneous MultiThreading (SMT) to improve the occupancy of their internal execution units through a sustained stream of instructions coming from more than one thread. We target the AMD Bulldozer and IBM POWER7 processors as case studies for specific hardware-oriented performance optimizations that increase the variety of instructions sent to each core to maximize the occupancy of all its execution units. WorkOver, presented in this article, improves thread scheduling by increasing the performance of floating point-intensive workloads on Linux-based operating systems. WorkOver is a user-space monitoring tool that automatically identifies FPU-intensive threads and schedules them in a more efficient way without requiring any patches or modifications at the kernel level. Our measurements using standard benchmark suites show that speedups of up to 20% can be achieved by simply allowing WorkOver to monitor applications and schedule their threads, without any modification of the workload.

DOI10.1016/j.future.2013.06.015
Citation Key105
Refereed DesignationRefereed